In semiconductor devices, elimination of the formation defect of a wire, a via, a contact plug and others is an issue in order to obtain high reliability. As the formation defect due to a process caused with a high probability, a defect related to a contact plug is cited. Such a defect is as an embedding defect at a bottom of the contact plug and a defect due to a high resistance because of alteration or others.
When the formation defect of the contact plug is inspected, for example, a method of inspecting conduction between the contact plug and the semiconductor substrate is known, the method using a device formed for the inspection and being performed by irradiating a TEG (Test Elemental Group) including a configuration with connection between the contact plug and the semiconductor substrate with an electron ray. This method is called a VC (Voltage contrast) inspection.
Japanese Patent Application Laid-Open Publication No. H09-63994 (Patent Document 1) describes that a bulk region in which a support substrate is exposed by removing a buried oxide film is provided in a scribe line of a wafer including an SOI (Silicon On Insulator) substrate in order to suppress charge up. This document does not describe provision of an element structure in the bulk region.
Japanese Patent Application Laid-Open Publication No. 2003-172766 (Patent Document 2) describes that the TEG having the same configuration as that of an SRAM (Static Random Access Memory) is formed in the scribe line of the wafer in order to acquire electric characteristics of the SRAM. The Patent Document 2 does not describe usage of the SOI substrate. Also, these Patent Document 1 and Patent Document 2 do not describe provision of the TEG used for the VC inspection.